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4 ghz to 18 ghz divide-by-8 prescaler ADF5002 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features divide-by-8 prescaler high frequency operation: 4 ghz to 18 ghz integrated rf decoupling capacitors low power consumption active mode: 30 ma power-down mode: 7 ma low phase noise: ?153 dbc/hz single dc supply: 3.3 v compatible with adf4xxx plls temperature range: ?40c to +105c small package: 3 mm 3 mm lfcsp applications pll frequency range extender point-to-point radios vsat radios communications test equipment general description the ADF5002 prescaler is a low noise, low power, fixed rf divider block that can be used to divide down frequencies as high as 18 ghz to a lower frequency suitable for input to a pll ic, such as the adf4156 or the adf4106 . the ADF5002 provides a divide-by-8 function. the ADF5002 operates from a 3.3 v supply and has differential 100 rf outputs to allow direct interface to the differential rf inputs of plls such as the adf4156 and adf4106 . functional block diagram divide by 8 bias ADF5002 ce gnd rfin vddx rfout rfout 100 ? 50? 100 ? 1pf 3pf 1pf 08753-001 figure 1.
ADF5002 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 4 ? esd caution .................................................................................. 4 ? pin configuration and function descriptions ..............................5 ? typical performance characteristics ..............................................6 ? evaluation board pcb ......................................................................7 ? pcb material stack-up ................................................................7 ? bill of materials ..............................................................................7 ? application circuit ............................................................................8 ? outline dimensions ..........................................................................9 ? ordering guide .............................................................................9 ? revision history 6 /10revision 0: initial version
ADF5002 rev. 0 | page 3 of 12 specifications vdd1 = vdd2 = 3.3 v 10%, gnd = 0 v; dbm referred to 50 ; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +105c. table 1. parameter min typ max unit test conditions/comments rf characteristics input frequency 4 18 ghz rf input sensitivity ?10 +10 dbm 4 ghz to 18 ghz output power ?10 ?5 dbm single-ended output connected into a 50 load ?7 ?2 dbm differential outputs connected into a 100 differential load output voltage swing 200 330 mv p-p peak-to-peak voltage swing on each single-ended output, connected into a 50 load 400 660 mv p-p peak-to-peak voltage swing on differential output, connected into a 100 differential load 1000 mv p-p peak-to-peak voltage swing on each single-ended output, no load condition phase noise ?153 dbc/hz input frequency (f in ) = 12 ghz, offset = 100 khz reverse leakage ?60 dbm rf input power (p in ) = 0 dbm, rf out = 4 ghz second harmonic content ?38 dbc third harmonic content ?12 dbc fourth harmonic content ?20 dbc fifth harmonic content ?19 dbc ce input input high voltage, v ih 2.2 v input low voltage, v il 0.3 v power supplies voltage supply 3.0 3.3 3.6 v i dd (i dd1 + i dd2 ) active 30 60 ma ce is high power-down 7 25 ma ce is low
ADF5002 rev. 0 | page 4 of 12 absolute maximum ratings table 2. parameter rating vddx to gnd ?0.3 v to +3.9 v rfin 10 dbm operating temperature range industrial (b version) ?40c to +105c storage temperature range ?65c to +150c maximum junction temperature 150c lfcsp thermal impedance junction-to-ambient ( ja ) 90c/w junction-to-case ( jc ) 30c/w peak temperature 260c time at peak temperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of 2 kv, human body model (hbm), and is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
ADF5002 rev. 0 | page 5 of 12 notes 1. nc = no connect. 2. the exposed paddle must be connected to gnd. g g pin configuration and fu nction descriptions pin 1 indicator 1 gnd 2 rfin 3 gnd 4 gnd 11 rfout 12 gnd 10 rfout 9gnd 5 nd 6 nc 7 ce 8 nd 15 vdd 1 16 gnd 14 vdd2 13 gnd top view (not to scale) ADF5002 08753-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 3, 4, 5, 8, 9, 12, 13, 16 gnd rf ground. all ground pins should be tied together. 2 rfin single-ended 50 input to the rf prescaler. this pin is ac-coupled internally via a 3 pf capacitor. 6 nc no connect. this pin can be left unconnected. 7 ce chip enable. this pin is active high. when ce is br ought low, the part enters power-down mode. if this functionality is not required, the pin can be left unco nnected because it is pulled up internally through a weak pull-up resistor. 10 rfout divided-down output of the prescaler. this pin has an internal 100 load resistor tied to vdd2 and an ac-coupling capacitor of 1 pf. 11 rfout complementary divided-down output of the prescaler. th is pin has an internal 100 load resistor tied to vdd2 and an ac-coupling capacitor of 1 pf. 14 vdd2 voltage supply for the output stage. this pin should be decoupled to ground with a 0.1 f capacitor in parallel with a 10 pf capacitor and can be tied directly to vdd1. 15 vdd1 voltage supply for the input stage and divider block. this pin should be decoupled to ground with a 0.1 f capacitor in parallel with a 10 pf capacitor. epad the lfcsp has an exposed paddle that must be connected to gnd.
ADF5002 rev. 0 | page 6 of 1 typical performance characteristics ? 5 ?10 ?15 ?25 ?35 ?45 ?50 2.4 3.0 3.6 harmonic power (dbm) vddx (v) ?60 ?50 ?40 ?30 ?20 ?10 0 2 0 5 10 15 25 20 30 input frequency (ghz) minimum input power (dbm) 8753-003 v dd = 3.0v v dd = 3.3v v dd = 3.6v 0 figure 3. rf input sensitivity 40 35 30 25 20 15 10 5 0 i ddx (ma) 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 vddx (v) 08753-004 i dd_in f in = 10ghz, p in = 0dbm i dd_out figure 4. i dd1 and i dd2 vs. vddx, f in = 10 ghz, p in = 0 dbm 0 ?2 ?4 ?6 ?8 ?10 ?14 ?18 ?12 ?16 output power (dbm) ?20 2.5 2.9 3.3 3.7 vddx (v) 3.9 2.7 3.1 3.5 08753-005 f in = 10ghz, p in = 0dbm figure 5. rf output power (single-ended) vs. vddx, f in = 10 ghz, p in = 0 dbm 2.7 3.3 ?20 ?30 ?40 first harmonic third harmonic fifth harmonic seventh harmonic eighth harmonic ninth harmonic eleventh harmonic 08753-006 figure 6. rf output harmonic content vs. vddx 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 05 output power (dbm) 10 20 30 15 25 input frequency (ghz) f in = 10ghz, v dd = 3.3v 8753-007 0 figure 7. rf output power vs. rf input frequency, f in = 10 ghz, v dd = 3.3 v
ADF5002 rev. 0 | page 7 of 1 08753-00 2 evaluation board pcb the evaluation board has four connectors as shown in figure 8 . the rf input connector (j4) is a high frequency precision sma connector from emerson. this connector is mechanically compatible with sma, 3.5 mm, and 2.92 mm cables. 8 figure 8. evaluation board silkscreentop view the evaluation board is powered from a single 3.0 v to 3.6 v supply, which should be connected to the j1 sma connector. the power supply can also be connected using the t3 (vddx) and t2 (gnd) test points. the differential rf outputs are brought out on the j2 and j3 sma connectors. if only one of the outputs is being used, the unused output should be correctly terminated using a 50 sma termination. the chip enable (ce) pin can be controlled using the t1 test point. if this function is not required, the test point can be left unconnected. pcb material stack-up the evaluation board is built using rogers ro4003c material (0.008 inch). rf track widths are 0.015 inch to achieve a controlled 50 characteristic impedance. the complete pcb stack-up is shown in figure 9 . fr4 prepreg 0.0372? 0.5oz (18m) finished copper rogers ro4003c laminate 0.008? r = 3.38. starting copper weight 0.5oz/0.5oz 1.5oz (53m) finished copper 0.5oz (18m) finished copper 1.5oz (53m) finished copper rogers ro4003c laminate 0.008? r = 3.38. starting copper weight 0.5oz/0.5oz 0.062? 0.003? copper to copper 08753-009 figure 9. evaluation board pcb layer stack-up bill of materials table 4. qty reference designator description supplier part number 1 c1 0.1 f, 0603 capacitor murata grm188r71h104ka93d 1 c2 10 pf, 0402 capacitor murata grm1555c1h100jz01d 3 j1, j2, j3 sma rf connector emerson 142-0701-851 1 j4 sma rf connector emerson 142-0761-801 3 t1, t2, t3 test points vero 20-2137 1 u1 ADF5002 rf prescaler analog devices, inc. ADF5002bcpz
ADF5002 rev. 0 | page 8 of 12 ADF5002 prescaler vdd1 rfout vdd2 adf4156 pll rf in a 10pf 0.1f cp 220? 330? 1.8nf 47nf 1k? rfin application circuit the ADF5002 can be connected either single-ended or differ- entially to any of the analog devices pll family of ics. it is recommended that a differential connection be used for best performance and to achieve maximum power transfer. the application circuit shown in figure 10 shows the ADF5002 used as the rf prescaler in a microwave 16 ghz pll loop. the ADF5002 divides the 16 ghz rf signal down to 2 ghz, which is input differentially into the adf4156 pll. an active filter topology, using the op184 op amp, is used to provide the wide tuning ranges typically required by microwave vcos. the positive input pin of the op184 is biased at half the adf4156 charge pump supply (v p ). this can be easily achieved using a simple resistor divider, ensuring sufficient decoupling close to the +in a pin of the op184 . this configuration, in turn, allows the use of a single positive supply for the op amp. alternatively, to optimize performance by ensuring a clean bias voltage, a low noise regulator such as the adp150 can be used to power the resistor divider network or the +in a pin directly. rfout rf in b gnd 820pf 1.8nf microwave vco rfout vtune 37 ? 150? 150? 1f v p /2 18 ? 6db attenuation pad 18? 16ghz out decoupling integrated op184 op amp 0 8753-010 figure 10. ADF5002 used as the rf prescaler in a microwave 16 ghz pll loop
ADF5002 rev. 0 | page 9 of 12 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.18 1.60 1.50 sq 1.40 111808-a 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.45 0.40 0.35 seating plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 11. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-18) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ADF5002bcpz ?40c to +105c 16-lead lead frame chip scale package (lfcsp_wq) cp-16-18 q1u ADF5002bcpz-rl7 ?40c to +105c 16-lead lead frame chip scale package (lfcsp_wq), 7 tape and reel cp-16-18 q1u eval-ADF5002eb2z evaluation board 1 z = rohs compliant part.
ADF5002 rev. 0 | page 10 of 12 notes
ADF5002 rev. 0 | page 11 of 12 notes
ADF5002 rev. 0 | page 12 of 12 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08753-0-6 /10(0)

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